The Design of a Static CMOS 16 Bit High Speed and Low Power Consumption Hybrid Adder Circuit Using Brent Kung Adder: A Recent Study

When compared to ripple deliver adders, a static sixteen Bit CMOS Brent kung adder structure was devised in this study, which boasted a higher speed and lower power consumption. The speed was enhanced by changing the shape and adding a Brent Kung adder, which is much quicker than a ripple supply adder and requires (28 transistor, Boolean exact judgement). DSP processors will benefit from these speed adders. With unique adders, time delays and power consumption are greatly decreased when using a 180nm Cadence device.

Author (s) Details

M. Ramana Reddy
Department of ECE, CBIT, Hyderabad, India.

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