Hybrid Signed Digit Arithmetic in Efficient Computing: A Comparative Approach to Performance Assay

In redundant representations, addition takes the same amount of time regardless of the operands’ word length. The adder is an essential building block in virtually all VLSI designs. The quality of a circuit’s ultimate output is determined by the efficiency of a hybrid adder, which can add an unsigned number to a signed-digit number. In this research, we used the combined effect of better adder architectures and signed digit representation of number systems to develop and compare the speed of adders by minimising the carry propagation time. The fundamental principle is to strike a compromise between the quick addition process’ execution time and the available area, which is sometimes very small. In this paper, we also tried to verify the various algorithms of signed digit and hybrid signed digit adders.

Author(S) Details

Vishal Awasthi
Department of Electronics & Communication Engineering, UIET, C.S.J.M. University, Kanpur-24, U.P., India.

Krishna Raj
Department of Electronics Engineering, H.B.T.I., Kanpur-24, U.P., India

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